1.完整项目描述和程序获取
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2.部分仿真图预览
3.算法概述
高斯白噪声信道在通信系统中具有重要意义，模拟此类信道有助于评估系统性能。本文提出的FPGA实现系统可以灵活地模拟不同信道条件，为通信系统的设计和测试提供有力支持。
4.部分源码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/08/17 14:13:20
// Design Name:
// Module Name: TEST
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module TEST();
reg i_clk;
reg i_rst;
reg signed[7:0]i_SNR;//根据质量得到当前帧类型:-10~50
reg signed[15:0]i_fre;
wire signed[15:0]i_real1;
wire signed[15:0]i_imag1;
wire signed[15:0]o_Rnoise1;
wire signed[15:0]o_Inoise1;
wire signed[15:0]o_real1;
wire signed[15:0]o_imag1;
reg signed[1:0]i_Idiff;
reg signed[1:0]i_Qdiff;
initial
begin
i_Idiff = 2'b00;
#1440
repeat(12500)
begin
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b01;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
#10 i_Idiff = 2'b00;
#30 i_Idiff = 2'b11;
end
$stop();
end
initial
begin
i_Qdiff = 2'b00;
#1440
repeat(12500)
begin
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b01;
#10 i_Qdiff = 2'b00;
#30 i_Qdiff = 2'b11;
end
$stop();
end
//测试信号源
wire signed[1:0] w_Inz=i_Idiff;
wire signed[1:0] w_Qnz=i_Qdiff;
//成型滤波
fiter uut1(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (w_Inz),
.o_dout (i_real1)
);
fiter uut2(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (w_Qnz),
.o_dout (i_imag1)
);
initial
begin
i_clk = 1'b1;
i_rst = 1'b1;
i_fre= 0;
i_SNR = 8'd0;
#1600
i_rst = 1'b0;
i_SNR = 0;
i_fre= 0;
#10000
i_SNR = 5;
i_fre= 0;
#10000
i_SNR = 15;
i_fre= 0;
#10000
i_SNR = 25;
i_fre= 0;
#10000
i_SNR = 45;
i_fre= 10;//1/2^15*100e6=3k频偏
end
always #5 i_clk=~i_clk;
AWGN_tops AWGN_tops_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_SNR (i_SNR),//根据质量得到当前帧类型:-10~50
.i_fre (i_fre),
.i_real1 (i_real1),
.i_imag1 (i_imag1),
.o_Rnoise1 (o_Rnoise1),
.o_Inoise1 (o_Inoise1),
.o_real1 (o_real1),
.o_imag1 (o_imag1)
);
endmodule
00_037m
---
